A multi-processor computer system includes multiple central processing units (CPUs) and memory resources. Some traditional architectures interconnect some or all of these system components through one or more shared busses. Because the busses are shared, communication between any two system components is limited by the bus bandwidth. Further, system components must communicate over a bus according to the system's bus contention rules, in order to avoid data collisions on the bus. The inherent latencies in bus-based systems limit their performance.
Other architectures interconnect CPUs and memory resources through crossbar switches. A crossbar switch is a circuit which may connect CPUs to each other and to various memory resources. A CPU may attach at any time to another CPU or to a memory resource through one or more crossbar switches, without contending for the connection. This type of architecture may be faster than a bus-based system, because each CPU and memory resource essentially has a “hard link” between them. Accordingly, contention issues are eliminated, and the system performance may be increased.
Like all types of circuits, crossbar circuits have limited connectivity. Accordingly, a single crossbar circuit may provide connections to a limited number of CPUs and memory resources. Accordingly, systems that include larger numbers of CPUs and memory resources may include multiple crossbar circuits. In such systems, an interconnection between a particular CPU and a particular memory resource may include multiple crossbar switches or “hops.” Each hop adds time to data transfers, and accordingly increases latency.
A goal for the interconnect between CPUs and memory resources is to provide sufficient bandwidth so that the interconnect is not the limiting performance factor when executing a program. Due to the memory bandwidth requirements of today's CPUs, this goal is difficult to meet. Therefore, current designs attempt to provide as much bandwidth as possible for the CPU and memory resource interconnect without violating other design constraints (e.g., cost, space, and power).